Simulation Results

/* variant: rle_decompress_bytes */

/* author: Степанов Арсений - P3318 - 368849 */

/* comment */

https://github.com/Armemius/ProcessorArchitectureExperiments/tree/main/src/m68k

/* assembler_code */

assembler_code =

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    .data
input_addr:      .word  0x80
output_addr:     .word  0x84
stack_top_pos:   .word  0x1000

    .text
    .org     0x100

_start:
    ; Setup stack pointer
    movea.l  stack_top_pos, A7               ; int* stack_top_pos
    movea.l  (A7), A7                        ; SP = *stack_top_pos

    ; Setup pointers
    movea.l  result_length, A6               ; A6 = result_length
    movea.l  result_bytes, A5                ; A5 = result_bytes

    ; Read input
    movea.l  input_addr, A0                  ; int** input_addr
    movea.l  (A0), A0                        ; int*  input_port = *input_addr
    move.l   (A0), D7                        ; int   bytes = *input_port

    ; D1 = bytes_left
    move.l   D7, D1
    cmp.l    0, D1
    ble      zero                            ; if (bytes_left == 0) zero()

    asr.l    1, D7                           ; int   cycles = bytes / 2

    ; // cycles = D7
    ; // data = D6
    ; // it = D5
    move.l   0, D5                           ; for (int it = 0; it < cycles; ++it) {
loop:
    cmp.l    D7, D5
    bge      output

    move.l   D5, D0
    and.l    1, D0
    cmp.l    0, D0
    bne      process
    movea.l  input_addr, A0
    movea.l  (A0), A0
    move.l   (A0), D6                        ;     if (it % 2 == 0) data = *input_port

    sub.l    2, D1
    cmp.l    1, D1                           ;     bytes_left -= 2
    beq      fail                            ;     if (bytes_left == 1) fail()

process:
    ; repeat_count = D4
    ; byte = D3
    move.l   D6, D4
    asr.l    16, D4
    move.b   D4, D3                          ; int byte = (data >> 16) & 0xFF
    asr.l    8, D4                           ; int repeat_count = data >> 24

    cmp.l    0, D4
    beq      fail

    add.l    D4, (A6)                        ; *result_length += repeat_count

    ; jt = D2
    move.l   0, D2
write_loop:
    cmp.l    D4, D2
    beq      write_loop_end
    move.b   D3, -(A5)
    add.l    1, D2
    jmp      write_loop


write_loop_end:
    asl.l    16, D6                          ; data = data << 16
    add.l    1, D5
    jmp      loop                            ; }

    ; it = D4
output:
    move.l   (A6), D4
    movea.l  output_addr, A1
    movea.l  (A1), A1
    move.l   D4, (A1)
    movea.l  result_bytes, A5

output_loop:
    cmp.l    0, D4                           ; while (it > 0) {
    ble      end
    move.l   -(A5), (A1)                     ;     *output_port = *(--result_bytes))
    sub.l    4, D4                           ;     it -= 4
    jmp      output_loop                     ; }

end:
    halt

    ; Subroutine to display zero bytes input
zero:
    movea.l  output_addr, A1
    movea.l  (A1), A1
    move.l   0, (A1)
    halt

    ; Subroutine to display failure
fail:
    movea.l  output_addr, A1
    movea.l  (A1), A1
    move.l   -1, (A1)
    halt

    ; Output results
    .data
.org             0x400
result_bytes:    .word  0
result_length:   .word  0

/* simulation_config */

simulation_config =

/* simulation_result */

$ date
2025-11-13 15:47:18.39381337 UTC
$ wrench --version
0.0.3.1 (af988d0) Wed Sep 10 19:03:23 2025 +0200
wrench --isa m68k /data/1718060c-87b3-4867-b768-3f3ff204a0d3/source.s -c /data/1718060c-87b3-4867-b768-3f3ff204a0d3/config.yaml
ExitSuccess

simulation_log =

/* testcase_result */

/app/variants/rle_decompress_bytes/1.yaml: ExitSuccess
/app/variants/rle_decompress_bytes/2.yaml: ExitSuccess
/app/variants/rle_decompress_bytes/3.yaml: ExitSuccess
/app/variants/rle_decompress_bytes/4.yaml: ExitSuccess
/app/variants/rle_decompress_bytes/5.yaml: ExitSuccess
/app/variants/rle_decompress_bytes/6.yaml: ExitSuccess
/app/variants/rle_decompress_bytes/7.yaml: ExitSuccess
/app/variants/rle_decompress_bytes/8.yaml: ExitSuccess

failed_test_case =

dump =

0:	input_addr
4:	output_addr
8:	stack_top_pos
256:	_start
318:	loop
378:	process
416:	write_loop
438:	write_loop_end
456:	output
480:	output_loop
508:	end
510:	zero
530:	fail
1024:	result_bytes
1028:	result_length
---
mem[0..3]: 	80 00 00 00	@"input_addr"
mem[4..7]: 	84 00 00 00	@"output_addr"
mem[8..255]: 	00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00	@"stack_top_pos"
mem[256..261]: 	MoveA {mode = Long, src = Immediate 8, dst = DirectAddrReg A7} 	@_start
mem[262..265]: 	MoveA {mode = Long, src = IndirectAddrReg 0 A7 Nothing, dst = DirectAddrReg A7}
mem[266..271]: 	MoveA {mode = Long, src = Immediate 1028, dst = DirectAddrReg A6}
mem[272..277]: 	MoveA {mode = Long, src = Immediate 1024, dst = DirectAddrReg A5}
mem[278..283]: 	MoveA {mode = Long, src = Immediate 0, dst = DirectAddrReg A0}
mem[284..287]: 	MoveA {mode = Long, src = IndirectAddrReg 0 A0 Nothing, dst = DirectAddrReg A0}
mem[288..291]: 	Move {mode = Long, src = IndirectAddrReg 0 A0 Nothing, dst = DirectDataReg D7}
mem[292..293]: 	Move {mode = Long, src = DirectDataReg D7, dst = DirectDataReg D1}
mem[294..299]: 	Cmp {mode = Long, src = Immediate 0, dst = DirectDataReg D1}
mem[300..305]: 	Ble {ref = 510}
mem[306..311]: 	Asr {mode = Long, src = Immediate 1, dst = DirectDataReg D7}
mem[312..317]: 	Move {mode = Long, src = Immediate 0, dst = DirectDataReg D5}
mem[318..319]: 	Cmp {mode = Long, src = DirectDataReg D7, dst = DirectDataReg D5} 	@loop
mem[320..325]: 	Bge {ref = 456}
mem[326..327]: 	Move {mode = Long, src = DirectDataReg D5, dst = DirectDataReg D0}
mem[328..333]: 	And {mode = Long, src = Immediate 1, dst = DirectDataReg D0}
mem[334..339]: 	Cmp {mode = Long, src = Immediate 0, dst = DirectDataReg D0}
mem[340..345]: 	Bne {ref = 378}
mem[346..351]: 	MoveA {mode = Long, src = Immediate 0, dst = DirectAddrReg A0}
mem[352..355]: 	MoveA {mode = Long, src = IndirectAddrReg 0 A0 Nothing, dst = DirectAddrReg A0}
mem[356..359]: 	Move {mode = Long, src = IndirectAddrReg 0 A0 Nothing, dst = DirectDataReg D6}
mem[360..365]: 	Sub {mode = Long, src = Immediate 2, dst = DirectDataReg D1}
mem[366..371]: 	Cmp {mode = Long, src = Immediate 1, dst = DirectDataReg D1}
mem[372..377]: 	Beq {ref = 530}
mem[378..379]: 	Move {mode = Long, src = DirectDataReg D6, dst = DirectDataReg D4} 	@process
mem[380..385]: 	Asr {mode = Long, src = Immediate 16, dst = DirectDataReg D4}
mem[386..387]: 	Move {mode = Byte, src = DirectDataReg D4, dst = DirectDataReg D3}
mem[388..393]: 	Asr {mode = Long, src = Immediate 8, dst = DirectDataReg D4}
mem[394..399]: 	Cmp {mode = Long, src = Immediate 0, dst = DirectDataReg D4}
mem[400..405]: 	Beq {ref = 530}
mem[406..409]: 	Add {mode = Long, src = DirectDataReg D4, dst = IndirectAddrReg 0 A6 Nothing}
mem[410..415]: 	Move {mode = Long, src = Immediate 0, dst = DirectDataReg D2}
mem[416..417]: 	Cmp {mode = Long, src = DirectDataReg D4, dst = DirectDataReg D2} 	@write_loop
mem[418..423]: 	Beq {ref = 438}
mem[424..425]: 	Move {mode = Byte, src = DirectDataReg D3, dst = IndirectAddrRegPreDecrement A5}
mem[426..431]: 	Add {mode = Long, src = Immediate 1, dst = DirectDataReg D2}
mem[432..437]: 	Jmp {ref = 416}
mem[438..443]: 	Asl {mode = Long, src = Immediate 16, dst = DirectDataReg D6} 	@write_loop_end
mem[444..449]: 	Add {mode = Long, src = Immediate 1, dst = DirectDataReg D5}
mem[450..455]: 	Jmp {ref = 318}
mem[456..459]: 	Move {mode = Long, src = IndirectAddrReg 0 A6 Nothing, dst = DirectDataReg D4} 	@output
mem[460..465]: 	MoveA {mode = Long, src = Immediate 4, dst = DirectAddrReg A1}
mem[466..469]: 	MoveA {mode = Long, src = IndirectAddrReg 0 A1 Nothing, dst = DirectAddrReg A1}
mem[470..473]: 	Move {mode = Long, src = DirectDataReg D4, dst = IndirectAddrReg 0 A1 Nothing}
mem[474..479]: 	MoveA {mode = Long, src = Immediate 1024, dst = DirectAddrReg A5}
mem[480..485]: 	Cmp {mode = Long, src = Immediate 0, dst = DirectDataReg D4} 	@output_loop
mem[486..491]: 	Ble {ref = 508}
mem[492..495]: 	Move {mode = Long, src = IndirectAddrRegPreDecrement A5, dst = IndirectAddrReg 0 A1 Nothing}
mem[496..501]: 	Sub {mode = Long, src = Immediate 4, dst = DirectDataReg D4}
mem[502..507]: 	Jmp {ref = 480}
mem[508..509]: 	Halt 	@end
mem[510..515]: 	MoveA {mode = Long, src = Immediate 4, dst = DirectAddrReg A1} 	@zero
mem[516..519]: 	MoveA {mode = Long, src = IndirectAddrReg 0 A1 Nothing, dst = DirectAddrReg A1}
mem[520..527]: 	Move {mode = Long, src = Immediate 0, dst = IndirectAddrReg 0 A1 Nothing}
mem[528..529]: 	Halt
mem[530..535]: 	MoveA {mode = Long, src = Immediate 4, dst = DirectAddrReg A1} 	@fail
mem[536..539]: 	MoveA {mode = Long, src = IndirectAddrReg 0 A1 Nothing, dst = DirectAddrReg A1}
mem[540..547]: 	Move {mode = Long, src = Immediate (-1), dst = IndirectAddrReg 0 A1 Nothing}
mem[548..549]: 	Halt
mem[550..1023]: 	( 00 )
mem[1024..1027]: 	00 00 00 00	@"result_bytes"
mem[1028..4095]: 	( 00 )	@"result_length"

/* comment: not found */

/* comment */

assembler_code =

simulation_config =

/* simulation_result */

simulation_log =

/* testcase_result */

failed_test_case =

dump =