Simulation Results

/* variant: sum_n */

/* author: Степанов Арсений - P3318 - 368849 */

/* comment */

https://github.com/Armemius/ProcessorArchitectureExperiments/tree/main/src/risc-iv-32

/* assembler_code */

assembler_code =

    .data
input_addr:      .word  0x80
output_addr:     .word  0x84
max_value:       .word  67999
failure_code:    .word  0xCCCCCCCC
stack_pos:       .word  0x1000

    .text
    .org 0x100
_start:
    ; Set up stack pointer
    lui      s7, %hi(stack_pos)
    addi     s7, s7, %lo(stack_pos)
    lw       s7, 0(s7)

    lui      t0, %hi(input_addr)
    addi     t0, t0, %lo(input_addr)
    lw       t0, 0(t0)                       ; int* input_port = *input_addr
    lw       t0, 0(t0)                       ; int n = *input_port

    lui      a0, %hi(max_value)
    addi     a0, a0, %lo(max_value)
    lw       a0, 0(a0)                       ; int max_value = *max_value

    ; // t0 = n
    ; // a0 = max_value = 67999
    ble      t0, zero, negative_or_zero      ; if (n <= 0) negative_or_zero
    ble      a0, t0, overflow                ; if (67999 < n) overflow

    jal      s6, calc_subroutine
    j        end

overflow:
    lui      t1, %hi(failure_code)
    addi     t1, t1, %lo(failure_code)
    lw       t1, 0(t1)                       ; int result = *failure_code;
    j        end
negative_or_zero:
    addi     t1, t1, -1                      ; int result = -1
end:
    lui      t0, %hi(output_addr)
    addi     t0, t0, %lo(output_addr)
    lw       t0, 0(t0)                       ; int* output_addr_const = &output_addr
    sw       t1, 0(t0)                       ; *output_addr_const = result
    halt

calc_subroutine:
    addi     s7, s7, -8
    sw       s6, 0(s7)

    mv       t1, t0                          ; // t1 = t0
    addi     t1, t1, 1                       ; // t1 = t1 + 1
    mul      t1, t1, t0                      ; // t1 = t1 * t0
    addi     t2, t2, 2                       ; // t2 = 1
    div      t1, t1, t2                      ; int result = t0 * t1 / t2 = n * (n + 1) / 2

    lw       s6, 0(s7)
    addi     s7, s7, 8
    jr       s6

/* simulation_config */

simulation_config =

/* simulation_result */

$ date
2025-11-13 15:45:48.39737541 UTC
$ wrench --version
0.0.3.1 (af988d0) Wed Sep 10 19:03:23 2025 +0200
wrench --isa risc-iv-32 /data/74f0faec-4412-4d87-9415-8f6920296343/source.s -c /data/74f0faec-4412-4d87-9415-8f6920296343/config.yaml
ExitSuccess

simulation_log =

/* testcase_result */

/app/variants/sum_n/1.yaml: ExitSuccess
/app/variants/sum_n/2.yaml: ExitSuccess
/app/variants/sum_n/3.yaml: ExitSuccess
/app/variants/sum_n/4.yaml: ExitSuccess
/app/variants/sum_n/5.yaml: ExitSuccess
/app/variants/sum_n/6.yaml: ExitSuccess
/app/variants/sum_n/7.yaml: ExitSuccess

failed_test_case =

dump =

0:	input_addr
4:	output_addr
8:	max_value
12:	failure_code
16:	stack_pos
256:	_start
312:	overflow
328:	negative_or_zero
332:	end
352:	calc_subroutine
---
mem[0..3]: 	80 00 00 00	@"input_addr"
mem[4..7]: 	84 00 00 00	@"output_addr"
mem[8..11]: 	9f 09 01 00	@"max_value"
mem[12..15]: 	cc cc cc cc	@"failure_code"
mem[16..255]: 	00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00	@"stack_pos"
mem[256..259]: 	Lui {rd = S7, k = 0} 	@_start
mem[260..263]: 	Addi {rd = S7, rs1 = S7, k = 16}
mem[264..267]: 	Lw {rd = S7, offsetRs1 = MemRef {mrOffset = 0, mrReg = S7}}
mem[268..271]: 	Lui {rd = T0, k = 0}
mem[272..275]: 	Addi {rd = T0, rs1 = T0, k = 0}
mem[276..279]: 	Lw {rd = T0, offsetRs1 = MemRef {mrOffset = 0, mrReg = T0}}
mem[280..283]: 	Lw {rd = T0, offsetRs1 = MemRef {mrOffset = 0, mrReg = T0}}
mem[284..287]: 	Lui {rd = A0, k = 0}
mem[288..291]: 	Addi {rd = A0, rs1 = A0, k = 8}
mem[292..295]: 	Lw {rd = A0, offsetRs1 = MemRef {mrOffset = 0, mrReg = A0}}
mem[296..299]: 	Ble {rs1 = T0, rs2 = Zero, k = 32}
mem[300..303]: 	Ble {rs1 = A0, rs2 = T0, k = 12}
mem[304..307]: 	Jal {rd = S6, k = 48}
mem[308..311]: 	J {k = 24}
mem[312..315]: 	Lui {rd = T1, k = 0} 	@overflow
mem[316..319]: 	Addi {rd = T1, rs1 = T1, k = 12}
mem[320..323]: 	Lw {rd = T1, offsetRs1 = MemRef {mrOffset = 0, mrReg = T1}}
mem[324..327]: 	J {k = 8}
mem[328..331]: 	Addi {rd = T1, rs1 = T1, k = -1} 	@negative_or_zero
mem[332..335]: 	Lui {rd = T0, k = 0} 	@end
mem[336..339]: 	Addi {rd = T0, rs1 = T0, k = 4}
mem[340..343]: 	Lw {rd = T0, offsetRs1 = MemRef {mrOffset = 0, mrReg = T0}}
mem[344..347]: 	Sw {rs2 = T1, offsetRs1 = MemRef {mrOffset = 0, mrReg = T0}}
mem[348..351]: 	Halt
mem[352..355]: 	Addi {rd = S7, rs1 = S7, k = -8} 	@calc_subroutine
mem[356..359]: 	Sw {rs2 = S6, offsetRs1 = MemRef {mrOffset = 0, mrReg = S7}}
mem[360..363]: 	Mv {rd = T1, rs = T0}
mem[364..367]: 	Addi {rd = T1, rs1 = T1, k = 1}
mem[368..371]: 	Mul {rd = T1, rs1 = T1, rs2 = T0}
mem[372..375]: 	Addi {rd = T2, rs1 = T2, k = 2}
mem[376..379]: 	Div {rd = T1, rs1 = T1, rs2 = T2}
mem[380..383]: 	Lw {rd = S6, offsetRs1 = MemRef {mrOffset = 0, mrReg = S7}}
mem[384..387]: 	Addi {rd = S7, rs1 = S7, k = 8}
mem[388..391]: 	Jr {rs = S6}
mem[392..4095]: 	( 00 )

/* comment: not found */

/* comment */

assembler_code =

simulation_config =

/* simulation_result */

simulation_log =

/* testcase_result */

failed_test_case =

dump =